Synopsys For Physical Design Of Asic Computer Science Essay

Synopsys For Physical Design Of Asic Computer Science Essay IC Compiler is the software package from Synopsys for Physical Design of ASIC. It provides necessary tools to complete the back end design of the very deep submicron designs. The inputs to the IC Compiler are: a gate-level netlist which can be from DC Compiler or third-party tools, a detailed floorplan which can be from previous Design Planning through IC Compiler or other third-party tools, timing constraints and other constraints, physical and timing libraries provided by manufacturer, and foundry-process data. IC Compiler generates a GDSII-format file as output ready for tape out of the chip. In addition, it is possible to export a Design Exchange Format (DEF) file of placed netlist data ready for a third-party router. IC Compiler uses a binary Synopsys Milkyway database, which can be used by other Synopsys tools based on Milkyway. [16] 4.2 User Interfaces IC Compiler can be used either with Shell interface (icc_shell) or with Graphical user interface (GUI). Shell interface is the command-line interface, which is used for batch mode, scripts, typing commands, and push-button type of operations. Graphical user interface (GUI) is an advanced graphical analysis and physical editing tool. Certain tasks, such as very accurately displaying the design and providing visual analysis tools, can only performed from the GUI. Also tool command language (Tcl), which is used in many applications in the EDA industry, is available to IC Compiler. Using Tcl, you can write reusable procedures and scripts. The IC Compiler design flow is an easy-to-use, single-pass flow that provides convergent timing closure. Figure 4.1 shows the basic IC Compiler design flow, which is centered around three core commands that perform placement and optimization (place_opt), clock tree synthesis and optimization (clock_opt), and routing and postroute optimization (route_opt). [16] icc1 Figure 4.1 IC Compiler Design Flow [21] For most designs, if the place_opt, clock_opt, and route_opt steps are followed, IC Compiler will provide optimal results. You can use IC Compiler to efficiently perform chip-level design planning, placement, clock tree synthesis and routing on designs with moderate timing and congestion challenges. To further improve the quality of results for your design you can use additional commands and switches for placement, clock tree synthesis, and routing steps that IC Compiler provides. IC Compiler design flow involves execution of following steps: 1. Set up and prepare the libraries and the design data. 2. Perform design planning and power planning. -Design planning is to perform necessary steps to create a floorplan, determine the size of the design, create the boundary and core area, create site rows for the placement of standard cells, set up the I/O pads. -Power planning, is to perform necessary steps to create a power plan to meet the power budget and the target leakage current. 3. Perform placement and optimization. IC Compiler placement and optimization uses enhanced placement and synthesis technologies to generate a legalized placement for leaf cells and an optimized design, which addresses and resolves timing closure issues for the provided design. You can supplement this functionality by optimizing for power, recovering area for placement, minimizing congestion, and minimizing timing and design rule violations. To perform placement and optimization, use the place_opt core command (or from GUI choose Placement menu and then Core Placement and Optimization sub-menu). 4. Perform clock tree synthesis and optimization. To perform the clock tree synthesis and optimization phase, use the command clock_opt (or choose Clock > Core Clock Tree Synthesis and Optimization in the GUI). IC Compiler clock tree synthesis and embedded optimization solve complicated clock tree synthesis problems, such as blockage avoidance and the correlation between preroute and postroute data. Clock tree optimization improves both clock skew and clock insertion delay by performing buffer sizing, buffer relocation, gate sizing, gate relocation, level adjustment, reconfiguration, delay insertion, dummy load insertion, and balancing of interclock delays. 5. Perform routing and postroute optimization. To perform routing and postroute optimization, use the route_opt core command (or choose Route > Core Routing and Optimization in the GUI). As part of routing and postroute optimization, IC Compiler performs global routing, track assignment, detail routing, search and repair, topological optimization, and engineering change order (ECO) routing. For most designs, the default routing and postroute optimization setup produces optimal results. If necessary, you can supplement this functionality by optimizing routing patterns and reducing crosstalk or by customizing the routing and postroute optimization functions for special needs. 6. Perform chip finishing and design for manufacturing tasks. IC Compiler provides chip finishing and design for manufacturing and yield capabilities that you can apply throughout the various stages of the design flow to address process design issues encountered during chip manufacturing. 7. Save the design. Save your design in the Milkyway format. This format is the internal database format used by IC Compiler to store all the logical and physical information about a design. [16] 4.3 How to Invoke the IC Compiler 1. Log in to the UNIX environment with the user id and password . 2. Start IC Compiler from the UNIX promt: UNIX$ icc_shell The xterm unix prompt turns into the IC Compiler shell command prompt. 3. Start the GUI. icc_shell> start_gui This window can display schematics and logical browsers, among other things, once a design is loaded. 4.4 Preparing the Design IC Compiler uses a Milkyway design library to store design and its associated library information. This section describes how to set up the libraries, create a Milkyway design library, read your design, and save the design in Milkyway format. These steps are explained in the following sections: à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Libraries à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Power and Ground Nets à ¢Ã¢â€š ¬Ã‚ ¢ Reading the Design à ¢Ã¢â€š ¬Ã‚ ¢ Annotating the Physical Data à ¢Ã¢â€š ¬Ã‚ ¢ Preparing for Timing Analysis and RC Calculation à ¢Ã¢â€š ¬Ã‚ ¢ Saving the Design 4.4.1 Setting Up the Libraries IC Compiler requires both logic libraries and physical libraries. The following sections describe how to set up and validate these libraries. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Logic Libraries: IC Compiler uses logic libraries to provide timing and functionality information for all standard cells. In addition, logic libraries can provide timing information for hard macros, such as RAMs. IC Compiler uses variables to define the logic library settings. In each session, you must define the values for the following variables (either interactively, in the .synopsys_dc.setup file, or by restoring the values saved in the Milkyway design library) so that IC Compiler can access the libraries: à ¢Ã¢â€š ¬Ã‚ ¢ search_path Lists the paths where IC Compiler can locate the logic libraries. à ¢Ã¢â€š ¬Ã‚ ¢ target_library Lists the logic libraries that IC Compiler can use to perform physical optimization. à ¢Ã¢â€š ¬Ã‚ ¢ link_library Lists the logic libraries that IC Compiler can search to resolve references. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Up the Physical Libraries: IC Compiler uses Milkyway reference libraries and technology (.tf) files to provide physical library information. The Milkyway reference libraries contain physical information about the standard cells and macro cells in your technology library. In addition, these reference libraries define the placement unit tile. The technology files provide information such as the names and characteristics (physical and electrical) for each metal layer, which are technology-specific. The physical library information is stored in the Milkyway design library. For each cell, the Milkyway design library contains several views of the cell, which are used for different physical design tasks. If you have not already created a Milkyway library for your design (by using another tool that uses Milkyway), you need to create one by using the IC Compiler tool. If you already have a Milkyway design library, you must open it before working on your design. This section describes how to perform the following tasks: à ¢Ã¢â€š ¬Ã‚ ¢ Create a Milkyway design library To create a Milkyway design library, use the create_mw_lib command (or choose File > Create Library in the GUI). à ¢Ã¢â€š ¬Ã‚ ¢ Open a Milkyway design library To open an existing Milkyway design library, use the open_mw_lib command (or choose File > Open Library in the GUI). à ¢Ã¢â€š ¬Ã‚ ¢ Report on a Milkyway design library To report on the reference libraries attached to the design library, use the -mw_reference_library option. icc_shell>report_mw_lib-mw_reference_library design_library_name To report on the units used in the design library, use the report_units command. icc_shell> report_units à ¢Ã¢â€š ¬Ã‚ ¢ Change the physical library information To change the technology file, use the set_mw_technology_file command (or choose File > Set Technology File in the GUI) to specify the new technology file name and the name of the design library. à ¢Ã¢â€š ¬Ã‚ ¢ Save the physical library information To save the technology or reference control information in a file for later use, use the write_mw_lib_files command (or choose File > Export > Write Library File in the GUI). In a single invocation of the command, you can output only one type of file. To output both a technology file and a reference control file, you must run the command twice. à ¢Ã¢â€š ¬Ã‚ ¢ Verifying Library Consistency: Consistency between the logic library and the physical library is critical to achieving good results. Before you process your design, ensure that your libraries are consistent by running the check_library command. [16] icc_shell> check_library 4.4.2 Setting Up the Power and Ground Nets IC Compiler uses variables to define names for the power and ground nets. In each session, you must define the values for the following variables (either interactively or in the .synopsys_dc.setup file) so that IC Compiler can identify the power and ground nets: à ¢Ã¢â€š ¬Ã‚ ¢ mw_logic0_net By default, IC Compiler VSS as the ground net name. If you are using a different name, you must specify the name by setting the mw_logic0_net variable. à ¢Ã¢â€š ¬Ã‚ ¢ mw_logic1_net By default, IC Compiler uses VDD as the power net name. If you are using a different name, you must specify the name by setting the mw_logic1_net variable. 4.4.3 Reading the Design IC Compiler can read designs in either Milkyway or ASCII (Verilog, DEF, and SDC files) format. à ¢Ã¢â€š ¬Ã‚ ¢ Reading a Design in Milkyway Format à ¢Ã¢â€š ¬Ã‚ ¢ Reading a Design in ASCII Format 4.4.4 Annotating the Physical Data IC Compiler provides several methods of annotating physical data on the design: à ¢Ã¢â€š ¬Ã‚ ¢ Reading the physical data from a DEF file To read a DEF file, use the read_def command (or choose File > Import > Read DEF in the GUI). icc_shell> read_def -allow_physical design_name.def à ¢Ã¢â€š ¬Ã‚ ¢ Reading the physical data from a floorplan file A floorplan file is a file that you previously created by using the write_floorplan command (or by choosing Floorplan > Write Floorplan in the GUI). icc_shell> read_floorplan floorplan_file_name à ¢Ã¢â€š ¬Ã‚ ¢ Copying the physical data from another design To copy physical data from the layout (CEL) view of one design in the current Milkyway design library to another, use the copy_floorplan command (or choose Floorplan > Copy Floorplan in the GUI). [16] icc_shell> copy_floorplan -from design1 4.4.5 Preparing for Timing Analysis and RC Calculation IC Compiler provides RC calculation technology and timing analysis capabilities for both preroute and postroute data. Before you perform RC calculation and timing analysis, you must complete the following tasks: à ¢Ã¢â€š ¬Ã‚ ¢ Set up the TLUPlus files You specify these files by using the set_tlu_plus_files command (or by choosing File > Set TLU+ in the GUI). icc_shell> set_tlu_plus_files -tech2itf_map ./path/map_file_name.map -max_tluplus ./path/worst_settings.tlup -min_tluplus ./path/best_settings.tlup à ¢Ã¢â€š ¬Ã‚ ¢ (Optional) Back-annotate delay or parasitic data To back-annotate the design with delay information provided in a Standard Delay Format (SDF) file, use the read_sdf command (or choose File > Import > Read SDF in the GUI). To remove annotated data from design, use the remove_annotations command. à ¢Ã¢â€š ¬Ã‚ ¢ Set the timing constraints At a minimum, the timing constraints must contain a clock definition for each clock signal, as well as input and output arrival times for each I/O port. This requirement ensures that all signal paths are constrained for timing. To read a timing constraints file, use the read_sdc command (or choose File > Import > Read SDC in the GUI). icc_shell> read_sdc -version 1.7 design_name.sdc à ¢Ã¢â€š ¬Ã‚ ¢ Specify the analysis mode Semiconductor device parameters can vary with conditions such as fabrication process, operating temperature, and power supply voltage. The set_operating_conditions command specifies the operating conditions for analysis. à ¢Ã¢â€š ¬Ã‚ ¢ (Optional) Set the derating factors If your timing library does not include minimum and maximum timing data, you can perform simultaneous minimum and maximum timing analysis by specifying derating factors for your timing library. Use the set_timing_derate command to specify the derating factors. à ¢Ã¢â€š ¬Ã‚ ¢ Select the delay calculation algorithm By default, IC Compiler uses Elmore delay calculation for both preroute and postroute delay calculations. For postroute delay calculations, you can choose to use Arnoldi delay calculation either for clock nets only or for all nets. Elmore delay calculation is faster, but its results do not always correlate with the PrimeTime and PrimeTime SI results. The Arnoldi calculation is best used for designs with smaller geometries and high resistive nets, but it requires more runtime and memory. [16] 4.4.6 Saving the Design To save the design in Milkyway format, use the save_mw_cel command (or choose File > Save Design in the GUI). [16] CHAPTER 5: Design Planning 5.1 Introduction Design planning in IC Compiler provides basic floorplanning and prototyping capabilities such as dirty-netlist handling, automatic die size exploration, performing various operations with black box modules and cells, fast placement of macros and standard cells, packing macros into arrays, creating and shaping plan groups, in-place optimization, prototype global routing analysis, hierarchical clock planning, performing pin assignment on soft macros and plan groups, performing timing budgeting, converting the hierarchy, and refining the pin assignment. Power network synthesis and power network analysis functions, applied during the feasibility phase of design planning, provide automatic synthesis of local power structures within voltage areas. Power network analysis validates the power synthesis results by performing voltage-drop and electromigration analysis. [16] Figure 5.1 IC Compiler Design Planning [21] 5.2 Tasks to be performed during Design Planning à ¢Ã¢â€š ¬Ã‚ ¢ Initializing the Floorplan à ¢Ã¢â€š ¬Ã‚ ¢ Automating Die Size Exploration à ¢Ã¢â€š ¬Ã‚ ¢ Handling Black Boxes à ¢Ã¢â€š ¬Ã‚ ¢ Performing an Initial Virtual Flat Placement à ¢Ã¢â€š ¬Ã‚ ¢ Creating and Shaping Plan Groups à ¢Ã¢â€š ¬Ã‚ ¢ Performing Power Planning à ¢Ã¢â€š ¬Ã‚ ¢ Performing Prototype Global Routing à ¢Ã¢â€š ¬Ã‚ ¢ Performing Hierarchical Clock Planning à ¢Ã¢â€š ¬Ã‚ ¢ Performing In-Place Optimization à ¢Ã¢â€š ¬Ã‚ ¢ Performing Routing-Based Pin Assignment à ¢Ã¢â€š ¬Ã‚ ¢ Performing RC Extraction à ¢Ã¢â€š ¬Ã‚ ¢ Performing Timing Analysis à ¢Ã¢â€š ¬Ã‚ ¢ Performing Timing Budgeting à ¢Ã¢â€š ¬Ã‚ ¢ Committing the Physical Hierarchy à ¢Ã¢â€š ¬Ã‚ ¢ Refining the Pin Assignment 5.3 Initializing the Floorplan The steps in initializing the floorplan are described below. à ¢Ã¢â€š ¬Ã‚ ¢ Reading the I/O Constraints: To load the top-level I/O pad and pin constraints, use the read_io_constraints command. à ¢Ã¢â€š ¬Ã‚ ¢ Defining the Core and Placing the I/O Pads: To define the core and place the I/O pads and pins, use the initialize_floorplan command. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Rectilinear-Shaped Blocks: Use the initialize_rectilinear_block command to create a floorplan for rectilinear blocks from a fixed set of L, T, U, or cross-shaped templates. These templates are used to determine the cell boundary and shape of the core. To do this, use initialize_rectilinear_block -shape L|T|U|X. à ¢Ã¢â€š ¬Ã‚ ¢ Writing I/O Constraint Information: To write top-level I/O pad or pin constraints, use the write_io_constraints command. Read the Synopsys Design Constraints (SDC) file (read_sdc command) to ensure that all signal paths are constrained for timing. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Cell Rows: To add cell rows, use the add_row command. à ¢Ã¢â€š ¬Ã‚ ¢ Removing Cell Rows: To remove cell rows, use the cut_row command. à ¢Ã¢â€š ¬Ã‚ ¢ Saving the Floorplan Information: To save the floorplan information, use the write_floorplan command. à ¢Ã¢â€š ¬Ã‚ ¢Writing Floorplan Physical Constraints for Design Compiler Topographical Technology: IC Compiler can now write out the floorplan physical constraints for Design Compiler Topographical Technology (DC-T) in Tcl format. The reason for using floorplan physical constraints in the Design Compiler topographical technology mode is to accurately represent the placement area and to improve timing correlation with the post-place-and-route design. The command syntax is: write_physical_constraints -output output_file_name -port_side [16] Figure 5.2 Floor Plan After Initialization [21] 5.4 Automating Die Size Exploration This section describes how to use MinChip technology in IC Compiler to automate the processes exploring and identifying the valid die areas to determine smallest routable, die size for your design while maintaining the relative placement of hard macros, I/O cells, and a power structure that meets voltage drop requirements. The technology is integrated into the Design Planning tool through the estimate_fp_area command. The input is a physically flat Milkyway CEL view. 5.5 Handling Black Boxes Black boxes can be represented in the physical design as either soft or hard macros. A black box macro has a fixed height and width. A black box soft macro sized by area and utilization can be shaped to best fit the floorplan. To handle the black boxes run the following set of commands. set_fp_base_gate estimate_fp_black_boxes flatten_fp_black_boxes create_fp_placement place_fp_pins create_qtm_model qtm_bb set_qtm_technology -lib library_name create_qtm_port -type clock $port report_qtm_model write_qtm_model -format qtm_bb report_timing qtm_bb 5.6 Performing an Initial Virtual Flat Placement The initial virtual flat placement is very fast and is optimized for wire length, congestion, and timing. The way to perform an initial virtual flat placement is described below. à ¢Ã¢â€š ¬Ã‚ ¢ Evaluating Initial Hard Macro Placement: No straightforward criteria exist for evaluating the initial hard macro placement. Measuring the quality of results (QoR) of the hard macro placement can be very subjective and often depends on practical design experience. à ¢Ã¢â€š ¬Ã‚ ¢ Specifying Hard Macro Placement Constraints: Different methods can be use to control the preplacement of hard macros and improve the QoR of the hard macro placement. Creating a User-Defined Array of Hard Macros Setting Floorplan Placement Constraints On Macro Cells Placing a Macro Cell Relative to an Anchor Object Using a Virtual Flat Placement Strategy Enhancing the Behavior of Virtual Flat Placement With the macros_on_edge Switch Creating Macro Blockages for Hard Macros Padding the Hard Macros à ¢Ã¢â€š ¬Ã‚ ¢ Padding the Hard Macros: To avoid placing standard cells too close to macros, which can cause congestion or DRC violations, one can set a user-defined padding distance or keepout margin around the macros. One can set this padding distance on a selected macros cell instance master.During virtual flat placement no other cells will be placed within the specified distance from the macros edges. [16] To set a padding distance (keepout margin) on a selected macros cell instance master, use the set_keepout_margin command. à ¢Ã¢â€š ¬Ã‚ ¢ Placing Hard Macros and Standard Cells: To place the hard macros and standard cells simultaneously, use the create_fp_placement command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Floorplan Editing: IC Compiler performs the following floorplan editing operations. Creating objects Deleting objects Undoing and redoing edit changes Moving objects Changing the way objects snap to a grid Aligning movable objects 5.7 Creating and Shaping Plan Groups This section describes how to create plan groups for logic modules that need to be physically implemented. Plan groups restrict the placement of cells to a specific region of the core area. This section also describes how to automatically place and shape objects in a design core, add padding around plan group boundaries, and prevent signal leakage and maintain signal integrity by adding modular block shielding to plan groups and soft macros. The following steps are covered for Creating and Shaping Plan Groups. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Plan Groups: To create a plan group, create_plan_groups command. To remove (delete) plan groups from the current design, use the remove_plan_groups command. à ¢Ã¢â€š ¬Ã‚ ¢ Automatically Placing and Shaping Objects In a Design Core: Plan groups are automatically shaped, sized, and placed inside the core area based on the distribution of cells resulting from the initial virtual flat placement. Blocks (plan groups, voltage areas, and soft macros) marked fix remain fixed; the other blocks, whether or not they are inside the core, are subject to being moved or reshaped. To automatically place and shape objects in the design core, shape_fp_blocks command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Padding to Plan Groups: To prevent congestion or DRC violations, one can add padding around plan group boundaries. Plan group padding sets placement blockages on the internal and external edges of the plan group boundary. Internal padding is equivalent to boundary spacing in the core area. External padding is equivalent to macro padding. To add padding to plan groups, create_fp_plan_group_padding command. To remove both external and internal padding for the plan groups, use the remove_fp_plan_group_padding command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Block Shielding to Plan Groups or Soft Macros: When two signals are routed parallel to each other, signal leakage can occur between the signals, leading to an unreliable design. One can protect signal integrity by adding modular block shielding to plan groups and soft macros. The shielding consists of metal rectangles that are created around the outside of the soft macro boundary in the top level of the design, and around the inside boundary of the soft macro. To add block shielding for plan groups or soft macros, use the create_fp_block_shielding command. To remove the signal shielding created by modular block shielding, use the remove_fp_block_shielding command. [16] 5.8 Performing Power Planning After completed the design planning process and have a complete floorplan, one can perform power planning, as explained below. à ¢Ã¢â€š ¬Ã‚ ¢ Creating Logical Power and Ground Connections: To define power and ground connections, use the connect_pg_nets command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Power and Ground Rings: It is necessary to add power and ground rings after doing floorplanning. To add power and ground rings, use the create_rectangular_rings command. à ¢Ã¢â€š ¬Ã‚ ¢ Adding Power and Ground Straps: To add power and ground straps, use the create_power_straps command. à ¢Ã¢â€š ¬Ã‚ ¢ Prerouting Standard Cells: To preroute standard cells, use the preroute_standard_cells command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Low-Power Planning for Multithreshold-CMOS Designs: One can perform floorplanning for low-power designs by employing power gating. Power gating has the potential to reduce overall power consumption substantially because it reduces leakage power as well as switching power. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Power Network Synthesis: As the design process moves toward creating 65-nm transistors, issues related to power and signal integrity, such as power grid generation, voltage (IR) drop, and electromigration, have become more significant and complex. In addition, this complex technology lengthens the turnaround time needed to identify and fix power and signal integrity problems. By performing power network synthesis one can preview an early power plan that reduces the chances of encountering electromigration and voltage drop problems later in the detailed power routing. To perform the PNS, one can run the set of following commands. [16] synthesize_fp_rail set_fp_rail_constraints set_fp_rail_constraints -set_ring set_fp_block_ring_constraints set_fp_power_pad_constraints set_fp_rail_region_constraints set_fp_rail_voltage_area_constraints set_fp_rail_strategy à ¢Ã¢â€š ¬Ã‚ ¢ Committing the Power Plan: Once the IR drop map meets the IR drop constraints, one can run the commit_fp_rail command to transform the IR drop map into a power plan. à ¢Ã¢â€š ¬Ã‚ ¢ Handling TLUPlus Models in Power Network Synthesis: Power network synthesis supports TLUPlus models. set_fp_rail_strategy -use_tluplus true à ¢Ã¢â€š ¬Ã‚ ¢ Checking Power Network Synthesis Integrity: Initially, when power network synthesis first proposes a power mesh structure, it assumes that the power pins of the mesh are connected to the hard macros and standard cells in the design. It then displays a voltage drop map that one can view to determine if it meets the voltage (IR) drop constraints. After the power mesh is committed, one might discover problem areas in design as a result of automatic or manual cell placement. These areas are referred to as chimney areas and pin connect areas. To Check the PNS Integrity one can run the following set of commands. set_fp_rail_strategy -pns_commit_check_file set_fp_rail_strategy -pns_check_chimney_file set_fp_rail_strategy -pns_check_chimney_file pns_chimney_report set_fp_rail_strategy -pns_check_hor_chimney_layers set_fp_rail_strategy -pns_check_chimney_min_dist set_fp_rail_strategy -pns_check_pad_connection file_name set_fp_rail_strategy -pns_report_pad_connection_limit set_fp_rail_strategy -pns_report_min_pin_width set_fp_rail_strategy -pns_check_hard_macro_connection file_name set_fp_rail_strategy -pns_check_hard_macro_connection_limit set_fp_rail_strategy -pns_report_min_pin_width à ¢Ã¢â€š ¬Ã‚ ¢ Analyzing the Power Network: One perform power network analysis to predict IR drop at different floorplan stages on both complete and incomplete power nets in the design. To perform power network analysis, use the analyze_fp_rail command. To add virtual pads, use the create_fp_virtual_pad command. To ignore the hard macro blockages, use the set_fp_power_plan_constraints command. à ¢Ã¢â€š ¬Ã‚ ¢ Viewing the Analysis Results: When power and rail analysis are complete, one can check for the voltage drop and electromigration violations in the design by using the voltage drop map and the electromigration map. One can save the results of voltage drop and electromigration current density values to the database by saving the CEL view that has just been analyzed. à ¢Ã¢â€š ¬Ã‚ ¢ Reporting Settings for Power Network Synthesis and Power Network Analysis Strategies: To get a report of the current values of the strategies used by power network synthesis and power network analysis by using the report_fp_rail_strategy command. [16] 5.9 Performing Prototype Global Routing One can perform prototype global routing to get an estimate of the routability and congestion of the design. Global routing is done to detect possible congestion hot spots that might exist in the floorplan due to the placement of the hard macros or inadequate channel spacing. To perform global routing, use the route_fp_proto command. 5.10 Performing Hierarchical Clock Planning This section describes how to reduce timing closure iterations by performing hierarchical clock planning on a top-level design during the early stages of the virtual flat flow, after plan groups are created and before the hierarchy is committed. One can perform clock planning on a specified clock net or on all clock nets in the design. à ¢Ã¢â€š ¬Ã‚ ¢ Setting Clock Planning Options: To set clock planning options, use the set_fp_clock_plan_options command. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Clock Planning Operations: To perform clock planning operations, use the compile_fp_clock_plan command. à ¢Ã¢â€š ¬Ã‚ ¢ Generating Clock Tree Reports: To generate clock tree reports, use the report_clock_tree command. à ¢Ã¢â€š ¬Ã‚ ¢ Using Multivoltage Designs in Clock Planning: Clock planning supports multivoltage designs. Designs in multivoltage domains operate at various voltages. Multivoltage domains are connected through level-shifter cells. A level-shifter cell is a special cell that can carry signals across different voltage areas. à ¢Ã¢â€š ¬Ã‚ ¢ Performing Plan Group-Aware Clock Tree Synthesis in Clock Planning: With this feature, clock tree synthesis can generate a clock tree that honors the plan groups while inserting buffers in the tree and prevent new clock buffers from being placed on top of a plan group unless they drive the entire subtree inside that particular plan group. This results in a minimum of clock feedthroughs, which makes the design easier to manage during partitioning and budgeting. [16] 5.11 Performing In-Place Optimization In-place optimization is an iterative process that is based on virtual routing. Three types of optimizations are performed: timing improvement, area recovery, and fixing DRC violations. T

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Hamlet: Hamlet The Idealist In Hamlet, Elsinore is a society which people are seen acting in a deceitful manner in order to gain personal measures and prestige. These people mask their true in intentions to acquire selfish desires. In doing so they develop a theme of the discrepancy between the way things appear and their true realities. Hamlet, on the other hand, is an honest, moral individual trapped in this deceitful society. Hamlet is faced with the dilemma to either lower himself to their level by utilizing deception, or leave wrongs unrighted by remaining true to himself. In Hamlet, the theme of appearance versus reality is prevalent in Hamlet's decision between his morals and his father as he decides to utilize the deceit of his society, starts recognizing it in others and finally in using it to avenge his father. When Hamlet is introduced he is seen acting as he feels and this is what prevents him from repaying in kind for his father's murder. Hamlet grieves over the loss of his father so long and intensely that no one understands, for Gertrude and Claudius tell him he needs to move on like they have done, yet Hamlet can't understand this. His actions are reflections of his true feelings while the rest of his peers seem to be ignoring their grief. When Hamlet finds out that he is supposed to kill Claudius for his father he becomes distraught. This is because Hamlet's morals won't allow him to kill even if it releases Old Hamlet from his purgatory. He later realizes that he must start appearing differently than usual in order to carry out his father's word. Hamlet decides to put on an "antic disposition" and in doing so has started becoming deceitful. He is trying to mask his true feelings in order to prepare himself for his dilemma. When Hamlet starts being deceitful he starts to recognize the deceit in others and how they make themselves appear differently from their realities. Hamlets decision to put on an "antic disposition" was not honest to himself but he felt that he must appear differently than he feels to fulfill his needs. Hamlet first recognizes the deceit in Claudius after his father visits. Claudius committed the sin of fratricide (especially horrendous in this Christian society); but was now enjoying the fruits of his sin at the cost of his community. He tricked Elsinore into thinking he was a good king who stepped in to save the kingdom, yet in reality he was the cause of all the trouble. Claudius knew he had done wrong, for he later laments his action, but was now

Team Behavior Essays -- Business, Organizational Structure

Team Behavior The organizational structure is compromised of groups and teams. Organizational behavior theory examines individual and group behavior types in relation to performance, organizational structure, ethics, and conflict resolution. Extensive research has been done in the field of development and application of team behavior and the positive or negative impact it has on accomplishing organizational objectives. Tuckman’s team development theory, Mintzberg’s study of organizational politics, and The Ringelmann effect will be examined. These theories provide insight into the complexities inherent in group structure and the mechanisms organizations need to minimize dysfunctional activities. The term group and team are used interchangeably for this discussion although they do not have the same meaning. A team consists of a number of people committed to common goals. Teams help organizations enhance performance, reduce costs, and provide employees with a sense of dignity and self-fulfillment. A team’s composition is formal or informal, its effectiveness is predicated, in part, on an organizations’ culture and the personalities and roles of the team members. . Group Development 1. There are critics of the five†stage group development model. Their main point is that this presentation of a group’s development is too static. Do you agree with this criticism? Why? The Tuckman stages of team development focuses on building and developing teams by analyzing team behavior. The first stage is forming. Group members get to know each other. Tuckman calls this the â€Å"ice breaking† stage. The second stage is storming. In this stage conflicts and power struggles occur as individuals compare views. The third stage is nor... ...for their outputs. Conflict among teams exists in organizations. Conflict aligned with business objectives and fosters positive employee performance (functional conflict), should be encouraged by management. However, conflict between groups that impede business objectives (dysfunctional conflict), must be confronted immediately and eliminated by management. Another form of conflict in organizations is resistance to authority. Mintzberg (1983) describes these tendencies as political games. The whistleblower game attempts to bring about organizational change by exposing practices or behaviors an individual perceives as unethical and in violation of the law. Organizations with sound ethical standards embrace valid whistle-blowing, however, most organizations view whistle-blowing negatively and impose various methods of retaliation against the individual.

Bullying in the Philippines Essay

A few years ago, the idea that bullying in the Philippines is widespread was thought to be a joke. People thought that bullying wasn’t as bad as the bullying seen in American teen movies. We Filipinos thought that bullying isn’t even an issue here in our country. But recently, our eyes have been opened to the reality that bullying is a bigger issue in the Philippines than we originally thought. Out of nowhere, cases like the online bullying of Christopher Lao, Tito Sotto, and the most recent case, Pauline Salvosa. It can really make us wonder how a country we thought of as Bully-free can produce such acts of hate towards another. If people can bully others to this extent even the public’s eye, what about during their everyday lives where they are unsupervised and much freer to do whatever they want, whenever they want to do it; whether it is in the workplace, home, and in this study’s case, at the school. This study will focus on that. Statement of the Problem The purpose of this study is to develop a deeper understanding of the effects that in-class bullying can have on a high school teenager. It is important to study this issue because school is one of the foundations of the formation of an individual’s character. A major challenge confronting DepEd here in the Philippines is the rising number of cases of in-class bullying in the country despite their efforts to stop the occurrence of In-Class Bullying. Sotto, Lao, and Salvosa were all greatly affected by the bullying. Salvoso and Lao were greatly depressed by the verbal attacks, Sotto even created a law against it. If these three victims were really shaken by the bullying, what about the other people who go through bullying every day in their neighborhood, in the workplace, and in school? What about the children in school who also experience this every day? If three grown adults are all affected by this, how much greater does it affect the kids who are still developing their inte llectual and emotional quotients? This will be the focus of the study, and the following questions will be answered: 1.) How much of their self-concept is affected by the bullying? 2.) What actions do these teens consider as bullying? 3.) Are there other factors that affect the development of the Self-Concept other than bullying? 4.) How much of their self-concept has changed over the period of time that the individual has been bullied? 5.) How do the teens cope with the bullying? Research Objectives The study will aim to discover more about how bullying schools affect the formation of one’s self-concept. It will help us in analyzing the effects, thus giving us more ways to deal with it. The research will help open a new dimension of understanding for bullies, parents, and most importantly, the victims themselves, on how to approach the issue of bullying in schools and it will help pave the way in developing a better idea of how to handle a bullying situation. This study will also help us see how big an issue bullying has become here in Baguio city. In order to accomplish these objectives, a survey and a conversational analysis of interviews will be carried out. The survey’s aim is to formulate a universal definition of what the students deem as â€Å"bullying†, while the interviews will help the study determine how the students are affected by in-class bullying. Significance of the Study Bullying is becoming a rather big issue here in the Philippines and this study will help us understand the gravity of the issue that in-class bullying gives. There have been many cases of bullying here in the Philippines, even if we exclude the cyber-bullying cases. The Department of Education has even released a statement about the alarming increase of bullying cases in the country. It is imperative to know why this is happening and how it can be mitigated. The significance of this study is that it may help researchers may use this research’s findings as basis a related research topic. This study might even encourage these future researchers to delve deeper in the issue and create a more detailed and in-depth version of the research topic. It will also serve as basis in the study of the issues related to bullying, the self-concept, and the interpersonal communication patterns of individuals. The study will also provide more in-depth view of the issue of bullying because it focuses on a condition vital to the formation of one’s self-concept. Through this study, students will become aware of the great effects that bullying can have on others and this can help reduce the occurrence of sever bullying cases. Finally, the results of this study will provide some insights and information on how much bullying can change an individual’s view of himself/herself, how it can affect the way they interact with others, and how it c an change their view of the world they live in. Scope and Delimitations The scope of the study will focus on 3rd year – 4th year male and female high school students in Baguio city who are enrolled in schools here in Baguio. These schools are the University of Baguio Science High School. The study does not include students who do not have a junior standing in class. The study will not also focus on the schools that are not enrolled in the top three high schools in Baguio city. This study will not also include out of school teens.

Analyse the causes of the 1848 revolution in France Essay

Analyse the causes of the 1848 revolution in France. With the ascension of Louis-Phillipe to the throne in July 1830, after the abdication of Charles X he appeared to have many factors in his favour that would seem to warrant a successful monarch and long standing regime. However, after 14 years the monarch, Louis-Phillipe, felt forced into a position where he had to abdicate, why then did the regime collapse so suddenly and unexpectedly? Especially after it had overcome so many early difficulties to establish itself in the minds of the French as an acceptable form of government. I believe the answer lies in a number of factor/causes. Long Term Causes Notably, one of the greatest weaknesses of the monarchy was the fact that Louis-Phillipe could claim no right to the throne of France. The French Tradition concerning the crown was that of heredity right, and had occurred so for centuries, being based, it was claimed, on the will of God. Therefore, although disliked no one could dispute the right of the Bourbons to occupy the throne of France. Louis-Phillipe had no such divine right as there was no belief that the legitimate monarch should be replaced by one of his relatives if he became unpopular. On what basis, then, was he king? There only appear to be three basis’s for a regime; hereditary right, the will of the people or the force of arms. Louis-Phillipe fulfilled none of these criteria. Indeed, the Orleaninst Monarchy was merely a useful compromise clutched at by desperate land owners who feared for their welfare in context of the future. The only way such forms of government can survive is if they manage to continue con vincing their nation that they have the moral right to be in power and in so doing inspire confidence in their supporters. Other long-term causes of Louis-Phillipe eventual downfall can be traced to his policies, both foreign and domestic. What must be remembered is that for the previous five hundred years France had been the most powerful nation in Europe, a heroic and glorious past in which the French placed great importance in. This had ended with napoleons defeat at the hands of the fourth coalition of European powers who had felt that their safety had been placed in question. This, napoleons final defeat, had occurred fifteen years previous and sufficient time had lapsed for the French people to yearn a return to their glorious past and a reinstatement of their empire. However, Louis-Phillipe thought differently, ignoring his past (as a young man he was a refugee abroad which led him to view active/aggressive foreign policy with suspicion) and his natural caution and desire for peace, one has to take into account the fact that the other major European Powers were determined not to let France endanger the security of the other European states again. The king realized that it was likely that any provocation the Powers would attempt to impose their will upon France as they had done in 1815. He recognised the precarious position he was in therefore his highest priority was to avoid a general European war where he was sure to be opposed by Austria, Russia, Prussia and Britain. Evidence of this opinion came in the form of the Belgium question. Belgium previously of the French empire had been annexed to the Netherlands in an attempt to create a buffer to future French expansion. The Belgium’s were not happy with this situation and so rebelled. They were successful. There was general fear throughout Europe that France would then again annex Belgium, but this did not happen. France did not intervene even though Louis-Phillipe’s son was offered the crown. Instead, France worked closely with Britain to ensure the independence of Belgium. Later in Spain there was a power struggle, an area considered to be Frances sphere of influence, but again Louis-Phillipe tried to gain no unfair advantage in the area. This behaviour of the French king was abnormal in the eyes of the French and wholly disappointing as again and again he refused to gain international advantage. In the late 1830’s a foreign crisis emerged that would make the French people feel more than disappointment. The Ottoman Empire was an empire that was struggling. The only way it managed to maintain its control was by establishing local rulers who had relative freedom as long as they respected the suzerainty of the Sultan in Constantinople. However, one leader emerged, Mehemet Ali of Egypt that had almost as much power as the Sultan himself. This pleased the French as Ali was a client of theirs using a lot of their technology and intelligence. The European powers were displease with this and wanted to limit Ali’s powers. Thiers, the leading minister, began an obstructionist policy hoping that Ali would resolve matters in his own way, Thiers even implied it would be an issue that France would go to was over. Unfortunately Britain called Frances bluff as Britain and Russia forced Ali to accept their terms. Louis-Phillipe was humiliated as he wasn’t prepared to risk a war with Britain and Russia; he dismissed Thiers and had to accept national humiliation. This specific incident led to enormous displeasure and discontent among the French people. They felt that in backing down Louis-Phillipe had acted dishonourably and had humiliated the country. Furthermore, the subsequent friendship that evolved with Britain (a situation which Louis-Phillipe felt would be favourable to his position in Europe) added more salt to the wounds. France was playing a junior partner to Britain, the traditional enemy. Louis-Phillipe was in a position where he could do no right. He wasn’t in the position to adopt an aggressive foreign policy (that is aside from the fact that he didn’t want to) which disappointed his subjects and in the scenario where he did become active he adopted positions tha t led to even more humiliation than inactivity would have bestowed. Another aspect of Louis-Phillipe’s reign that could of led to his downfall can be rooted in his domestic policy. Again here inactivity was favoured by the king. Once the regime was established and certain basic rules changed to the kings liking the king’s view was that everything was working well so there was no use in tampering with it. Almost, that the system was beyond improvement. Unfortunately for the king, this was not a widely shared view. The main bone of discontent was concerning the current voting system. Many hankered for a reform especially as there was emerging a new class, a group of men who considered themselves to be part of the social elite and yet who didn’t have the right to vote. Their cause was championed by the Legislative assembly (with Thiers an ardent supporter) a situation which made life more difficult for the king and his government. Another reason for the eventual collapse of the July monarchy can be traced back to the actual person of the king. By 1843 the king had reached his 70th birthday and although fit and alert he was, decidedly old and traits that he had exhibited earlier on in life became more pronounced. His talkativeness became something to be endured, he avoided making decisions altogether being satisfied with the current situation, His public appearances became less which meant he couldn’t create and maintain personal loyalties, significantly he stopped reviewing the National Guard in 1840, what Louis-Phillipe couldn’t see was that he was leaving a vacuum that could easily be filled be someone else on the occasion of a crisis. However these weren’t his only problems for the king one of his other problems was that he failed to play the part of the grand and great king that was traditional in France. He dull and boring, to be honest, he lived like a bourgeoisie merchant doing much for himself, wandering through Paris unattended; he was not the inaccessible monarch of previously. He looked and dressed in an undistinguished manner. This led to the claim that the king was insufficiently different from the ordinary man to be worth having as king. Short Term Causes One of the major problems that surrounded the Revolution of 1848 was the current economic depression. Due to Industrial Revolution Paris had grown considerably which, even when the economy was healthy, created problems of poverty and poor living conditions. By 1846 there was widespread unemployment; tens of thousands of people were living in poverty or near starving. Also, around the same time a social conscience had begun to develop among the upper classes and the opinion was that something must be done. The king responded with his usual stoicism and stubbornness in that he felt that nothing could be done. This isolated some of his natural supporters and disillusioned those who thought that the July monarchy would be a flexible and responsive regime. There were many opponents of Guizot in Parliament, many of whom wanted to see him ousted form power. (NB. They wanted to achieve power for themselves not overthrow the king) One way which the felt effective was the organization of banquets to champion the cause of electoral reform. They arranged a series of local meeting to whip up popular support. Instead the reformers lost control as they were taken over by extreme republicans who desired the overthrowing of the regime. Consequently the meeting were banned and made illegal. There was one due to take place in Paris on 22 February 1848 but subsequently it was illegal. A march took its place. When Louis-Phillipe then called on the National Guard he recognized their reluctance and realized he judged the general mood wrongly. He lost his nerve. He dismissed Guizot in order to mollify the opposition but this instead gave hope to the agitators. The next day troops then fired on a good natured crowd killing 80. The Republicans used this to whip up anger and mobilize a mob in Paris. On 24 February 1848 Louis-Phillipe abdicated. In a situation as complex as that of the Revolution of 1848 with so many interdependent causes it is foolish to attempt to satisfy such a wide ranging issue with one simple answer. There was a fundamental weakness in the July Monarchy in that it seemed to have no right to the throne what was unfortunate for Louis-Phillipe was that there were already alternative forms of government available if the current one became unpopular. Furthermore, his changing personality was leaving a vacuum that could easily be filled be someone else on the occasion of a crisis. These both led to the king’s support being considerable diminished at a time when it was most need. Moreover The king’s lifestyle contributed to the widespread feeling that the July monarchy had outlived its usefulness: it was not that Louis-Phillipe’s lifestyle and personality turned friends into enemies; rather, they contributed to the slump n moral which left the way open to those who passionately wanted change. As well as this his both unsuccessful domestic and foreign led to a more hostile general feeling towards the king as well as contributing to the internal upheaval that eventually led to the kings unseating. In the immediate events leading to the king’s abdication Louis-Phillipe’s â€Å"senile imbecility† (A. de Tocqueville) had a large part to play. His loss of nerve lost many of his last supporters, he failed to stand firm and weather a modest storm. His handling of the situation and especially his failure to call the army which might well have saved him eventually led to his downfall. He allowed a small molehill to become a mountain for no strong reason. It is difficult to assess which of these factors played the greatest role, for, all of the long term factors appear of equal importance, on a par also with the backdrop of economic depression and social consciousness that was concurrent at the time however the questions still remains whether these on their own would have been enough to make a successful revolution and if whether the king had acted correctly and strongly, he would not have fallen It seems it was the kings inactivity that pervaded every part of his professional and personal life (foreign and domestic policy, personality and lifestyle and ultimately in the last days leading up to his abdication) that eventually l ed to his downfall. (Felt that this wasn’t a satisfactory conclusion, found it hard to articulate here, how could I improve it, there seemed to be so many possibilities) Use ready made alternative forms of govment in conclusion to show why fist point was important. Domestic policy – if their had been an electorate reform the regime would have won the cative support of the ‘new group’ Personality- he was lifestyle- they Hort term- Louis-Phillipes lack of stubbornessdismayed his supporters who say this as an indication that the end was near and nobody wants to support a lost acuse . Louis-Phillipe was still in the position to use the army and stand strong but the lack of support shown by the National Guard seemed to have b

Process of Education Essay

I thank the reason why the Process of Education is do difficult to attain is because people don’t honesty know what education is. Like, what is education, what does education mean, what does being educated mean, how far can an education take you in life, are there different types of educations, etc. I thank the minute everyone understands what it means to be educated or what education is. It won’t be hard for anyone to apprehend the Process of Education. If someone doesn’t understand the Educational Process how are they going to attain the information they receive from it. To fully take in the information you receive from the Educational Process you first have to know what education is? That could be another reason why people struggle with attaining the information from the Educational Process. Indeed, it is a lot to take in but the more you know the better off you will be and will understand it better. Education is the process of receiving or giving systematic instruction, esp. in a school or university. Knowing what education means will help a person exceed life expectations. The more you know the better off you’ll be. People should not only attain the knowledge to help them get by in life they should let their education take them further. Some people would rather just know what they need to know but if they really sit back and think â€Å"what if I expanded what I knew and learned something else other than what I already know†? How much easier it would be for them to attain knowledge and hold on to it. The Process of Education can be a start for some people to learn how to further their education. The Process of Education can best be describing as learning processes that will not only help you excel in your field of studies but also in your everyday life. It is a process that is ideally; interested in the material to be learned that is best stimulus to learning. The first object of any act of learning, over and beyond the pleasure it may give, is that it should serve us in the future. Learning should not only take us somewhere, it should allow us later to go further more easily. I found that learning a  subject involves three almost simultaneous processes. First, there is acquisition of new information — often information that runs counter to or is a replacement for what the person has previously known. A second aspect of learning may be called transformation — the process of manipulating knowledge to make it fit new tasks. Transformation comprises the ways we deal with information in order to go beyond it. A third aspect of learning is evaluation — checking whether the way we have manipulated information is adequate to the task. Not knowing the three processes to learning a subject may cause a change in a person mind to not want to learn the Process of Education and will make that person less interested in the Educational Process. It is very difficult to attain the Process of Education but the minute it’s understood the easier it will be to learn everything that is needed to learn. There will be a lot of people who would have wished they had understood the Educational Process and took their education to the limits. With an education in more than one study there’s no telling how far you can go, skies the limits. The more you know about the Process of Education the more you’re going to want to know and let soak in.

Wish You Well by David Baldacci

Character development is an important part of all novels. A character's mindset can change throughout the story as they go through events that may change there mindset. In Wish You Well by David Baldacci, Oz's personality and attitude change from the beginning to the end of the novel. His point of view alone effects the story. As the book starts off Oz is a little immature boy. He is not self efficient and relies completely on his mother Amanda and his older sister Lou. â€Å"Fortunately, his fearful cries would be replaced by a smile when Oz would at last focused on her, and she would want to hold her son always, keep him safe always. (Baldacci p. 4) Amanda had protected Oz his entire life and made him feel a sense of attachment. He never had to make his own decisions or face an event where his hope or faith was challenged. Until the car accident, his mother was severely injured and his father was killed. â€Å"Oz reached for his mother, incomprehension the only thing between the little boy and possibly fatal panic. † (Baldacci p. 14) This was the first and only time in the story that we see Oz in panic. Lou being older feels she understood more about the world and life than Oz. She had loved her father but clearly did not have the same type of relationship with her mother. After the accident and her father was dead, Lou seemed to get a negative outlook. She never once had a positive thought that possibly her mother could might get better and regain consciousness. Oz on the other hand never lost his faith. He always though positively. Throughout the novel Oz makes comment to his grandmother, diamond, and Lou that his mother could and was getting better. His love for her was so strong that even though deep down he knew the reality of her healing was not likely, he would do whatever he could to make it possibly come true. Oz thinks that wishing for his mother to regain her health at the wishing well will make her better. â€Å"I wish that my mother will wake up and love me again. He paused and then added solemnly, And Lou too. † (Baldacci p. 131) Oz truly cared about his mother and sister and risked his fear to try and make them all happy again. He was truly a caring character who changes from being a shy innocent boy. Into a caring self confident young man. Lou and Oz both loved each other and there mother. However, each characters point of view was different regarding the citation. Lou was kind of angry and tried to think about things realistic. She knew the odds of her mother getting well and there family going back to normal was limited. She realized it and tried to move on. As opposed to Oz who hoped and wished that his mother and Lou would get better and things could go back to the way they were. In the end even though both character's points of view where vastly different, they each helped each other get through some tragic events in the novel together, through love and perseverance.